For signal interfaces between devices terminators have been used, as described for instance in U.S. Pat. No. 4,748,426: entitled "Active termination circuit for computer interface use", granted May 31, 1988 to Alexander Stewart for Rodime PLC, in an active termination circuit for a computer interface for reducing line reflection of logic signals. Such terminators have used a first and second resistor combination to permanently connect to a signal line that couples a plurality of peripheral devices to one another. The other ends of the first and second resistors are connected through a switching device to a positive voltage supply line and to logic ground, respectively. When termination of multiple devices was required, a plurality of resistor combinations were provided but on/off control of the switch in this example was achieved by one control that is located remote from the termination circuit systems. Integrated circuit interconnection structures have also used precision terminating resistors, as illustrated by U.S. Pat. No. 4,228,369, granted in October, 1980 to Anantha et al. for IBM.
As will be illustrated for chip interconnection, when resistor terminators are used in thin film semiconductor integrated circuits such as those used in metal oxide semiconductors (e.g. CMOS) today, they create hot spots which cannot be adequately cooled, so such resistor terminator circuits which create hot spots cannot be used in metal oxide semiconductor applications to provide terminators for chip to chip connections on chips using IBM's new sub-micron MOS (CMOS) technologies where because of the high currents used in these networks it is difficult or impossible to meet all the cooling and reliability requirements required for commercial performance. It has become necessary to invent a solution to interfacing devices which can be used in such environments on chips, and used for terminators in networks of chips and devices where there is a need to transmit digital data therebetween without overshoot and undershoot in signal transmission between the chips and devices or systems. These connections need to operate at a faster speed, accommodating data rate speeds ranging into hundreds of Mhz and Ghz.
The creation of a terminator which particularly may be fabricated for high speed metal oxide semiconductor on insulator (MOS-soi) applications with triple wells in integrated circuits is needed.
It is therefore an object of the present invention to provide a terminator network adapted for MOS that can match the characteristic impedance of the line.
It is another object of the present invention to provide a terminator network which is fast and suitable for small signal swings and may also in a mixed technologies communication.
A further object of the present invention to provide a terminator network which has low current flow and low power consumption.
Still another objective of the present invention to provide a terminator network that provides ESD protection at the input of an attached circuit.
It is also an objective of the present invention to be able to switch into high impedance so that the driver can take control of the line and drive out for bi-directional data buses. Bi-directional data buses are used in all computer systems today.
It is still another objective of the present invention to be able to turnoff all currents to support the CMOS leakage test so that chips with defects can be found quickly and easily.
It is further an objective to be able to adjust the impedance of the terminator so that this circuit can have multiple usage.
It is another objective to be able to fine tune the terminator to have the desired reflection for the nets. This is to overcome any process tolerances.
It is also an objective of the present invention to be able to adjust the Vcenter voltage so that it can tune out any process mis-tracking of the pfet to nfets or mis-tracking of the power supplies from the sending to the receiving chip, and re-center the terminator voltage, so that maximum signal voltage can be obtain without creating skew between the zero and one logic levels.
A further object of the present invention to provide a terminator and receiver network which has low current flow and low power consumption.
It is also an objective to provide a receiver that can receive small signals properly. And have balanced noise tolerance between both logic levels.
Other objects and advantages of the invention will be apparent from the specification.